PHYSICAL DESIGN SOLUTIONS FOR THE DESIGN OF LOW POWER MULTI-TIER GATE-LEVEL MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS
Lin, Sheng-En David David
MetadataShow full item record
Three-dimensional (3-D) integration is emerging as a viable alternative to traditional scal- ing due to its potential to significantly reduce the on-chip wire length. 3-D integration technologies can be broadly classified into two groups, namely, through-silicon-via-based 3-D (TSV) and monolithic 3-D (M3-D) integration. TSV-based 3-D integration uses large through silicon vias to connect dies in the vertical direction, whereas M3-D integration uses tiny monolithic interdie vias (MIV). Due to the large size of the TSVs, the integration den- sity of the chips designed with TSVs is limited. Consequently, M3-D integration is being regarded as the holy grail for achieving ultra-high integration density. M3-D integration is expected to provide significantly higher degree of device density than TSV-based 3-D integration due mainly to its nano-scale interdie connections. By stacking more than two device layers (multi-tier) within a 3-D chip, further wire length reduction could be achieved, which can lead to additional performance and power bene- fits. However, in order to obtain these benefits, new physical design methodologies and algorithms are needed for designing multi-tier monolithic 3-D integrated circuits (MM3-D ICs). In this dissertation, we focus on new physical design solutions for the design of gate- level MM3-D ICs. First, we present a placement algorithm that optimizes dynamic power consumption for MM3-D ICs. By trading reduction in wire delay into further power saving, the placement algorithm reduces dynamic power more effectively than a state-of-the-art 3- D placer. Next, we present an efficient routing methodology for MM3-D routing. The routing methodology shows comparative routed wire length and with substantial run time improvement in comparison with a state-of-the-art routing methodology. In addition, we present a detailed investigation and analysis regarding the ideal number of dies we can stack for MM3-D ICs. Furthermore, we present algorithms to find multiple rectilinear steiner minimal trees (RSMTs) in both 2-D and 3-D. By finding multiple RSMTs, we open the gateway to further optimize the designs of MM3-D ICs and traditional 2-D ICs.